Many electronic integrated circuits, also known as "chips," are formed by a strategic placement and interconnection of selected electronic devices, such as transistors and the like, within a semiconductor substrate. The electronic devices are interconnected using an array of surface conductors carrying data signals through which the devices communicate. The electronic devices, however, must be sufficiently isolated from one another so that the signals in each respective electronic device do not interfere with and degrade the others' signal quality.
In semiconductor applications requiring relatively close placement of electronic devices, isolation is commonly provided by forming a recess (or "trench"), depicted as 14 and 16 (FIG. 2) between two active areas (or "area mesas") 11 (FIG. 2), upon which the electronic devices are located, and filling the trench with isolation material, generally a silicon oxide. Thus, the filled trench (oftentimes referred to as field oxide) then provides isolation between the electronic devices and the surface conductors. By way of further background, U.S. Pat. No. 4,842,675 describes a method of forming thermal LOCOS field oxide in combination with trenches.
A major problem encountered in refining this recessing technique involves maintaining planarity of the trench material so that materials, such as printed conductors, can be readily applied thereon using conventional methods (using, for instance, lithography). A poorly planarized trench typically includes uneven areas along the top of the trench such as oxide depressions and/or spikes. In applications requiring signal-carrying conductors to be printed on the filled trench, a poorly planarized trench causes signal discontinuities and often degrades the performance of the entire chip.
There have been numerous attempts to improve trench planarity in the prior art, each has fallen short of providing a trench that is adequately planarized for certain applications. Such processes are described, for example, in the background sections, and in the detailed description sections, of U.S. Pat. Nos. 5,130,268 (Liou et al.); 5,077,234 (Scoopo et al.); 5,006,482 (Kerbaugh et al.); and 4,892,614 (Chapman et al.).
In shallow trench isolation processes or local oxidation of silicon (LOCOS) isolation techniques, the field oxide that forms the isolation barrier is generally a deposit of silicon oxide formed from silane, for example, low pressure chemical vapor deposition (LPCVD) of tetraethorthosilane (TEOS). Unfortunately, the chemically deposited silicon dioxide etches roughly eight times faster (or if densified, 20% faster) than conventional thermal oxide used to form the sacrificial oxide layers. Thus, field oxide loss in the trench or isolation barrier during subsequent etch treatments of the sacrificial oxide is a particularly difficult problem. Precise control of the etching process is required to reduce field oxide over etch during the multiple cleaning and oxide strips during the fabrication process.
Accordingly, there is a need for an improved process of fabricating an isolation trench or LOCOS field oxide, which overcomes the above-mentioned deficiencies.